1. Field of Invention
The present invention relates to a method of manufacturing an electronic device and a method of manufacturing a semiconductor device.
2. Description of Related Art
To realize large-scale integration (LSI) of electronic devices, such as semiconductor devices, wiring lines have recently become multi-layered. In electronic devices having such multi-layered wiring lines, upper and lower wiring patterns with an interlayer insulating film disposed therebetween are electrically connected to each other through contact holes formed in the interlayer insulating film.
Here, in order to reduce the parasitic capacitance between the wiring lines, there have been proposed various methods of selecting a material having a low dielectric constant for the interlayer insulating film, making the interlayer insulating film thick, etc. Generally, silicon oxide is used as the material for the interlayer insulating film. However, if a silicon oxide film is thickened, film stress becomes larger, thereby causing cracks. Further, if the thick interlayer insulating film is formed on the wiring lines having an acute shape, constrictions (overhangs) are generated in the interlayer insulating film corresponding to the acute shape, so that there arises a problem that the wiring lines formed thereon is likely to short-circuit. Therefore, in order to avoid the influence due to the constrictions generated when the interlayer insulating film is formed on the wiring lines having the acute shape, for example, Japanese Unexamined Patent Application Publication No. 55-145356 discloses technology that phosphate glass is formed on the interlayer insulating film and then the wiring lines are formed on the glass.